The present invention relates to integrated circuit manufacturing and, more particularly, to integrated circuit interconnect formation. A major objective of the present invention is to provide for higher manufacturing yields and more reliable manufactured integrated circuit devices.
Progress in integrated circuit manufacture is generally associated with reductions in feature sizes; in fact, such progress can be roughly quantified as the minimum feature width definable by a given process technology. The features of interest are electrically active elements defined in a semiconductor substrate and conductive elements that provide access to and interconnection between the active elements. The minimum feature width for some of the earliest integrated circuits was a few microns; over the years, feature widths have dropped an order of magnitude. Reductions in feature width have allowed integrated circuit devices to be arranged closer together, providing greater functional density and higher operating speeds.
Although it has diminished along with feature width, feature thickness has not decreased as dramatically. Thus, relative to the feature width, deviations from planarity have become more severe. Such deviations from planarity pose a number of problems. For example, sharp focus is required to define small features photolithographically. Maximal sharpness occurs only at the focal plane of the photolithographic equipment, and focus becomes less sharp with distance from the focal plane. Where the nonplanarity is too severe, uniformly acceptable sharp focus cannot be achieved.
Planarization minimizes deviations from optimal sharpness, and thus is essential for defining minimal feature widths. Thus, a silica dielectric layer can be planarized so that a metal interconnect layer deposited thereon can be precisely patterned. (Silicas are a family of silicon-oxide materials including silicon dioxide and glasses, e.g., BPSG and SOG, commonly used as dielectrics in integrated circuits.) Chemical mechanical polishing (CMP), applicable to both conductors and dielectrics, has emerged as the planarized method of choice. While not fully understood, CMP of a silica layer is believed to involve continuous formation and abrasion of a hydrated silica sublayer, some of which remains in place once polishing has ended.
To the etchant and abrasives of the fresh slurry are added various polishing products from the integrated circuit, the polishing pad, and reaction products due to the action of the etchant. All of these spent slurry constituents are potential contaminants. A standard post-CMP clean uses a soft buffing pad with a solution including ammonium hydroxide and citric acid. This improves the surface finish and removes some particles. However, some metallic-ionic species typically remain to enter the hydrated silica sublayer and alter the electrical properties of the dielectric.
For large numbers of reliable integrated circuits to be manufactured, the structural and process materials involved must be precisely characterized. In general, this requires pure materials or pure materials that have been altered by the controlled introduction of impurities. While contamination is inevitable, even small amounts can impair the functioning, reliability, and/or lifetime of an integrated circuit. The susceptibility of integrated circuits to impairment by contamination has increased with decreasing feature sizes. In particular, the metallic contaminants resulting from CMP can impair the dielectric quality of the silica dielectric layers and increase their vulnerability to dielectric breakdown. Thus, to increase manufacturing yields and improve device reliability, it is necessary to address CMP-induced contamination more effectively.